FPGA Design Tutorial:

FPGA stands for Field Programmable Gate Array. There are many forms of devices which are field programmable. These are PAL, PLD, CPLD, and FPGA. These devices differ on their granularity, how the programming is accomplished etc. PAL, PLA and CPLD devices are usually smaller in capacity but more predictable in timing and they can be implemented with Sum-of-Products, Product-of-Sums or both. FPGA devices can be based on Flash, SRAM, EEPROM or Anti-Fuse connectivity. The most successful FPGA devices are based on SRAM. This is because all other memory types are much less dense in terms of area than SRAM. Also some types of connectivity are One-Time Programmable (i.e. Anti-Fuse) so they are not very flexible. SRAM based FPGAs have no maximum erase cycle limitations either.

FPGA development is in some sense similar to ASIC development. One can talk about Front-End Tools which can be Schematic Entry or an HDL (Hardware Description Language). Most common HDLs used for FPGA Design are Verilog and VHDL. After describing an FPGA design in an HDL, a tool called a Synthesizer which effectively converts Verilog, VHDL into the specific primitives which exist an an FPGA family. SRAM based FPGAs have Lookup-Tables which can be programmed to implement any function of N variables (usually 4~5) and Flip-Flops which can be programmed to implement different types of storage (JK, T, Latch, DFF with set and/or reset etc). 

After a device level netlist is generated with synthesis, one uses a back-end tool called Place & Route which is most of the time supplied by the device vendor (i.e. Xilinx or Altera). In contrast synthesis tools are usually supplied by third party vendors and even the ones packaged with vendors' toolset usually are restricted versions of third party tools. Most popular synthesis tools come from Synplicity, Exemplar, Cadence and Synopsys. DSPIA Inc. suggests Synplicity for FPGA development because of their high quality tools.

Most synthesis tools understand only a subset of HDLs which are synthesizable subsets. Up until recently these subsets weren't standardized and varied from vendor to vendor. These days there are efforts under way to standardize synthesizable Verilog and VHDL code.  A good site for Verilog or VHDL is EDA.ORG

From the P&R tool, one obtains a file which can be used to download onto an FPGA to program it with the hardware design described by the original HDL code. This download can be either done through a serial connection, a JTAG cable or programmed into a ROM and loaded into the FPGA every time power is applied. This is very roughly the flow of FPGA development. We'll go into more detail of every step and give simple examples using an Xilinx FPGA, Verilog and Synplify Synthesizer from Synplicity.

Here is a module which does binary to thermometer code conversion:

function [6:0] bin2ther;
input [2:0] bin;
    begin
    case (bin)
        3'h0: bin2ther = 7'b0000000;
        3'h1: bin2ther = 7'b0000001;
        3'h2: bin2ther = 7'b0000011;
        3'h3: bin2ther = 7'b0000111;
        3'h4: bin2ther = 7'b0001111;
        3'h5: bin2ther = 7'b0011111;
        3'h6: bin2ther = 7'b0111111;
        3'h7: bin2ther = 7'b1111111;
    endcase
end
endfunction

You can call this function in the following module:

module conv(in, out);
input [2:0] in;
output [7:0] out;

always @(in)
out = bin2ther(in);

endmodule

Now you're ready to do your first synthesis:

 

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