DSPIA Inc. has completed many consulting projects with FPGA implementations in the past. The following is a representative subset of the consulting designs we have delivered:

• High speed Adaptive Equalizers in Virtex-5 FPGA implemented using manual instantiation of DSP48E blocks.
• High Speed Interpolator Design For Xilinx Virtex FPGA Optimized using AMPL.
  • Polynomial Based Farrow Interpolator
  • Polynomial Coefficients Optimized with AMPL Script
• Verification of a Serializer/Deserializer With USB, Ethernet 10-BaseT on Xilinx Virtex FPGA using Verilog Test-bench.
  • Mapping of TSMC 0.25 micron design with embedded SRAM  and Flash memory to Virtex FPGA.
  • Modeling of Embedded SRAM and Flash with Virtex BlockRam memory.
  • Manual Floor-Planning to meet prototype timing requirements.
• Algorithm Development for Digital Clock Recovery using Kalman Filters in Matlab.
  • Fully Digital Clock Recovery using CORDIC, FARROW and Kalman Filters.
  • Timing Detector using 2x Over-sampled ADC.
  • ADC clock is non-synchronous to Transmit Clock.
  • Data Recovery done using Digital Interpolation with Farrow Filter.
  • Initial Filter Development In Matlab language.
  • C++ Fixed-Point Implementation of Kalman Filter.
  • Verilog Implementation of the Whole System
• High Performance DSP Equalizer prototyped on Xilinx Virtex FPGA using custom logic.
  • Developed for Standard Cell ASIC process.
  • LMS Adaptive Equalizer with Pipeline in Update.
  • Booth Multipliers merged with Multi-Input Adder
  • Wallace Tree Adder with 4-2 Compressor
  • Custom 4-2 Compressor Cells in Schematic Entry with Viewlogic
  • Design of PCB boards with Orcad Schematics and PADS PowerPCB for layout.
• Digital Controller logic for Serial ATA (SATA)
  • Implements SAPIS Interface
  • Implements SATA OOB signal detection, symbol alignment and TBC locking.
  • Adds Extra Vendor Control Signals for Debug and Status
  • Implemented with Standard Cell ASIC using Cadence First Encounter SOCE toolset for TSMC 130nm Process
• Digital Controller logic for PCI-Express
  • Implements PIPE Interface
  • Has Asynchronous Elasticity Buffer with SKIP symbol management
  • 8b10b encoder/decoder implementation, Symbol alignment.
  • Implemented with Standard Cell ASIC using Cadence First Encounter SOCE toolset for TSMC 130nm Process
• 33 MHz 32 Bit PCI Board With Xilinx Spartan-II FPGA and ATM SAR, PHY and PMD chips.
  • Development Done in Verilog.
  • Test-bench Development for Verification
  • PCI32 core utilization from Xilinx IP library.
  • Implementation of ATM UTOPIA Interface
  • Using Conexant ATM SAR, PHY and SDSL Data-Pump Chips
• 8051/2 compatible micro-controller with E/ISA/PC-104 bus interface on Altera 10K FPGA using Verilog.
  • Fully Compatible 8052 micro-controller
  • 12/24 Cycle Instruction Execution for Timing Compatibility.
  • Extra DPTR for fast memory copy and buffer management
  • Square-Root function for custom processing
  • Fast Multiply and Divide Arithmetic operators
  • Integrated with E/ISA PC-104 Interface using Dual Port Memory
  • Downloadable code using Embedded SRAM
• USB 1.1 Controller on Altera 10K FPGA in Verilog, VHDL mixed RTL.
  • Full Implementation of USB 1.1 Function.
  • Embedded DMA processing for low CPU utilization
  • DPLL Clock Recovery
  • State Machine Based USB Device Subset Implementation.
• Divider and Square Root Functions for Altera 10K FPGA in Verilog.
  • 16 by 8 Divider and 16 bit Integer Square Root function.
  • Retiring one bit per clock.
• Development and Verification of an 802.3 Ethernet MAC
  • Design of MAC architecture
  • Verilog RTL implementation
  • Debugging with Test Benches and Interoperability with Real 802.3 PHY
  • Generation of Packets and Delivery using Promiscuous Raw Mode with 10BASE-T PHY
• Coordinate transformation Algorithm using CORDIC sine/cosine in Verilog.
  • Area Optimized CORDIC unit for Sine/Cosine Calculation

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